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exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 1 sp3243e 3 driver/5 receiver intelligent +3.0v to +5.5v rs-232 transceivers the sp3243e products are 3 driver/5 receiver rs-232 transceiver solutions intended for portable or hand-held applications such as notebook and palmtop computers. the sp3243e includes one complementary receiver that remains alert to monitor an external device's ring indicate signal while the device is shutdown. the sp3243e and eb devices feature slew-rate limited outputs for reduced crosstalk and emi. the "u" and "h" series are optimized for high speed with data rates up to 1mbps, easily meeting the demands of high speed rs-232 applications. the sp3243e series uses an internal high-effciency, charge-pump power supply that requires only 0.1f capacitors in 3.3v operation. this charge pump and exar's driver architecture allow the sp3243e series to deliver compliant rs-232 performance from a single power supply ranging from +3.0v to +5.5v. the auto on-line ? feature allows the device to automatically "wake-up" during a shutdown state when an rs-232 cable is con - nected and a connected peripheral is turned on. otherwise, the device automatically shuts itself down drawing less than 1a. features meets true eia/tia-232-f standards from a +3.0v to +5.5v power supply interoperable with eia/tia-232 and adheres to eia/tia-562 down to a +2.7v power source auto on-line ? circuitry automatically wakes up from a 1a shutdown regulated charge pump yields stable rs-232 outputs regardless of v cc variations enhanced esd specifcations: + 15kv human body model + 15kv iec1000-4-2 air discharge + 8kv iec1000-4-2 contact discharge 250 kbps min. transmission rate (eb) 1000 kbps min. transmission rate (eu) ideal for high speed rs-232 applications description selection table now available in lead free packaging r 4 in 1 2 3 4 25 26 27 28 5 6 7 24 23 22 shutdo wn c2- v- r 1 in r 2 in r 3 in online c2+ c1- gnd v cc v+ st a tus t 1 in 8 9 10 11 18 19 20 21 12 13 14 17 16 15 r 5 out t 1 out t 2 out t 3 out t 3 in t 2 in r 4 out r 5 in r 3 out r 2 out r 1 out r 2 out sp3243e c1+ device power supplies rs-232 drivers rs-232 receivers external components auto on-line circuitry ttl 3- state # of pins data rate esd rating sp3243e +3.0v to +5.5v 3 5 4 capacitors yes yes 28 120 15kv sp3243eb +3.0v to +5.5v 3 5 4 capacitors yes yes 28 250 15kv sp3243eh +3.0v to +5.5v 3 5 4 capacitors yes yes 28 460 15kv sp3243eu +3.0v to +5.5v 3 5 4 capacitors yes yes 28 1000 15kv
2 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 note 1: v+ and v- can have maximum magnitudes of 7v, but their absolute difference cannot exceed 13v. absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifcations below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. v cc .......................................................-0.3v to +6.0v v+ (note 1).......................................-0.3v to +7.0v v- (note 1)........................................+0.3v to -7.0v v+ + |v-| (note 1)...........................................+13v i cc (dc v cc or gnd current)......................... + 100ma input voltages txin, online,shutdown, .....-0.3v to vcc +6.0v rxin................................................................... + 15v output voltages txout............................................................. + 13.2v rxout, status.......................-0.3v to (v cc +0.3v) short-circuit duration txout....................................................continuous storage temperature......................-65c to +150c unless otherwise noted, the following specifcations apply for v cc = +3.0v to +5.5v with t amb = t min to t max , c1 - c4 = 0.1 f. typical values apply at v cc = +3.3v or +5.0v and t amb = 25 c. power dissipation per package 28-pin soic (derate 12.7mw/ o c above +70 o c).........1000mw 28-pin ssop (derate 11.2mw/ o c above +70 o c)..........900mw 28-pin tssop (derate 13.2mw/ o c above +70 o c)......1059mw 32-pin qfn (derate 29.4mw/ o c above +70 o c)...........2352mw electrical characteristics parameter min. typ. max. units conditions dc characteristics supply current, auto on- line? 1.0 10 a all rxin open, online = gnd, shutdown = v cc , v cc = 3.3v t amb = 25 o c, txin = gnd or v cc supply current, shutdown 1.0 10 a shutdown = gnd, vcc = 3.3v, t amb = 25 o c, txin = vcc or gnd supply current auto on-line? disabled 0.3 1.0 ma online = shutdown = vcc, no load, v cc = 3.3v, t amb = +25 o c, txin = gnd or v cc logic inputs and receiver outputs input logic threshold low high 2.4 0.8 v v v cc = =3.3v or =5.0v, txin online, shutdown input leakage current + 0.01 + 1.0 a txin, online, shutdown, t amb = +25 o c, v in = 0v to v cc output leakage current + 0.05 + 10 a receivers disabled, v out = 0v to v cc output voltage low 0.4 v i out = 1.6ma output voltage high v cc -0.6 v cc -0.1 v i out = -1.0ma driver outputs output voltage swing + 5.0 + 5.4 v all driver outputs loaded with 3k? to gnd, t amb = +25 o c
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 3 unless otherwise noted, the following specifcations apply for v cc = +3.0v to +5.5v with t amb = t min to t max , c1 - c4 = 0.1 f. typical values apply at v cc = +3.3v or +5.0v and t amb = 25 c. electrical characteristics parameter min. typ. max. units conditions driver outputs (continued) output resistance 300 ? v cc = v+ = v- = 0v, v out = + 2v output short-circuit current + 35 + 60 ma v out = 0v output leakage current + 25 a v cc = 0v or 3.0v to 5.5v, v out = + 12v, drivers disabled receiver inputs input voltage range -15 15 v input threshold low 0.6 1.2 v vcc = 3.3v input threshold low 0.8 1.5 v vcc = 5.0v input threshold high 1.5 2.4 v vcc = 3.3v input threshold high 1.8 2.4 v vcc = 5.0v input hysteresis 0.3 v input resistance 3 5 7 k? auto on-line? circuitry characteristics (online = gnd, shutdown = vcc) 25c status output voltage low 0.4 v i out = 1.6ma status output voltage high v cc -0.6 v i out = -1.0ma receiver threshold to drivers enabled (t online ) 350 s figure 14 receiver positive or negative threshold to status high (t stsh ) 0.2 s figure 14 receiver positive or negative threshold to status low (t stsl ) 30 s figure 14 timing characteristics maximum data rate (u) (h) (b) ( - ) 1000 460 250 120 kbps r l = 3k?, c l = 250pf, one driver active r l = 3k?, c l = 1000pf, one driver active r l = 3k?, c l = 1000pf, one driver active r l = 3k?, c l = 1000pf, one driver active receiver propagation delay t phl t plh 0.15 0.15 s receiver input to receiver out - put, c l = 150pf receiver output enable time 200 ns normal operation receiver output disable time 200 ns normal operation driver skew (e, eb) (eh, eu) 100 50 500 100 ns | t phl - t plh | receiver skew 50 ns | t phl - t plh | transition-region slew rate (eh, eu) (e, eb) 6 90 30 v/s vcc = 3.3v, r l = 3k?, t amb = 25 c, measurements taken from -3.0v to +3.0v or +3.0v to -3.0v
4 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 unless otherwise noted, the following performance characteristics apply for v cc = +3.3v, 1000kbps data rate, all drivers loaded with 3k?, 0.1f charge pump capacitors, and t amb = +25 c. figure 2. transmitter output voltage vs. supply voltage for the sp3243eu figure 6. transmitter output voltage vs. load capacitance for the sp3243eb figure 1. transmitter skew vs. load capacitance 0 250 500 1000 1500 2000 200 150 100 50 0 load capacitance (pf) skew (ns) t1 at 500kbps t2 at 31.2kbps all tx loaded 3k // cload figure 3. transmitter output voltage vs. load capacitance for the sp3243eu figure 5. supply current vs. supply voltage for the sp3243eu figure 4. supply current vs. load capacitance for the sp3243eu typical performance characteristics 2.7 3 3.5 4 4.5 5 supply v oltage (v) 6 4 2 0 -2 -4 -6 1 d r i v e r a t 1 m b p s o t h e r d r i v e r s a t 6 2 . 5 k b p s a l l d r i v e r s l o a d e d w i t h 3 k / / 2 5 0 p f 25 20 15 10 5 0 2.7 3 3.5 4 4.5 5 supply v oltage (v d c ) 1 t ransmitter at 250kbps 2 t ransmitters at 15.6kbps all drivers loaded with 3k // 1000pf 0 250 500 1000 1500 2000 load capacitance (pf) t ransmitter output v oltage (v) 6 4 2 0 -2 -4 -6 1 tx at full data rat e 2 tx? s at1/16 data rat e 2mbps 1.5mbps 1mbps 2mbps 1.5mbps 1mbps 40 35 30 25 20 15 10 5 0 load capacitance (pf) 0 1000 2000 3000 4000 5000 2 5 0 k b p s 1 2 0 k b p s 2 0 k b p s 1 t r a n s m i t t e r a t f u l l d a t a r a t e 2 t r a n s m i t t e r s a t 1 5 . 5 k b p s a l l t r a n s m i t t e r s l o a d e s 3 k + l o a d c a p 6 4 2 0 -2 -4 -6 0 1000 2000 3000 4000 5000 txout + txout - load capacitance (pf) transmitter output voltage (v) supply current (ma) transmitter output voltage (v) supply current (ma)
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 5 unless otherwise noted, the following performance characteristics apply for v cc = +3.3v, 1000kbps data rate, all drivers loaded with 3k?, 0.1f charge pump capacitors, and t amb = +25 c. figure 7. slew rate vs. load capacitance typical performance characteristics 25 20 15 10 5 0 0 500 1000 2000 3000 4000 5000 load capacitance (pf) - slew + slew 1 t ransmitter at 250kbps 2 t ransmitter at 15.6kbps all drivers loaded 3k + load cap slew rate (v/s)
6 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 table 1. device pin description pin number name function sp3243e sp3243eucr qfn c1+ positive terminal of the voltage doubler charge-pump capacitor 28 28 v+ regulated +5.5v output generated by the charge pump 27 26 c1- negative terminal of the voltage doubler charge-pump capacitor 24 22 c2+ positive terminal of the inverting charge-pump capacitor 1 29 c2- negative terminal of the inverting charge-pump capacitor 2 31 v- regulated -5.5v output generated by the charge pump 3 32 r 1 in rs-232 receiver input. 4 2 r 2 in rs-232 receiver input 5 3 r 3 in rs-232 receiver input 6 4 r 4 in rs-232 receiver input 7 5 r 5 in rs-232 receiver input 8 6 r 1 out ttl/cmos receiver output 19 17 r 2 out ttl/cmos receiver output 18 16 r 2 out non-inverting receiver-2 output, active in shutdown 20 18 r 3 out ttl/cmos receiver output 17 15 r 4 out ttl/cmos receiver output 16 14 r 5 out ttl/cmos receiver output 15 13 status ttl/cmos output indicating online and shutdown status 21 19 t 1 in ttl/cmos driver input 14 12 t 2 in ttl/cmos driver input 13 11 t 3 in ttl/cmos driver input 12 10 online apply logic high to override auto on-line? circuitry keeping drivers acive (shutdown must also be logic high, refer to table 2) 23 21 t1 out rs-232 driver output 9 7 t2 out rs-232 driver output 10 8 t3 out rs-232 driver output 11 9 gnd ground 25 23 v cc +3.0v to +5.5v supply voltage 26 25 shutdown apply logic low to shutdown driver and charge pump. this overrides all auto on-line? circuitry and online (refer to table 2) 22 20 nc no connection - 1,24,27,30
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 7 figure 9. sp3243e qfn pinout confguration sp3243e v- c2- nc c2+ c1+ nc v+ v cc nc r 1 in r 2 in r 3 in r 4 in r 5 in t 1 out t 2 out t 3 out t 3 in t 2 in t 1 in r 5 out r 4 out r 3 out r 2 out 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nc gnd c1- online shutdow n status r 2 out r 1 out figure 8. sp3243e typical operating circuit sp3243e 28 24 2 1 27 3 26 5k ? 5k ? 5k ? 5k ? 5k ? gnd c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 9 10 11 4 5 6 7 8 rs-232 outputs rs-232 inputs ttl/cmos inputs ttl/cmos outputs to p super visor circuit 23 22 21 v cc v cc 25 t 1 in r 1 out r 1 in t 2 out r 2 out t 2 in t 3 in t 3 out t 1 out r 2 in r 3 in r 4 in r 5 in r 2 out r 3 out r 4 out r 5 out online shutdo wn st a tus
8 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 description the sp3243e transceivers meet the eia/tia- 232 and itu-t v.28/v.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. the sp3243e devices feature exar's proprietary and patented (u.s.-- 5,306,954) on-board charge pump cir - cuitry that generates 5.5v rs-232 voltage levels from a single +3.0v to +5.5v power supply. the sp3243eu devices can operate at a data rate of 1000kbps fully loaded. the sp3243e is a 3-driver/5-receiver device, ideal for portable or hand-held applications. the sp3243e includes one complementary always-active receiver that can monitor an external device (such as a modem) in shutdown. this aids in protecting the uart or serial controller ic by preventing forward biasing of the protection diodes where v cc may be disconnected. the sp3243e series is an ideal choice for power sensitive designs. the sp3243e devices feature auto on-line ? circuitry which reduces the power supply drain to a 1a supply current. in many portable or hand-held applications, an rs-232 cable can be disconnected or a connected peripheral can be turned off. under these condi - tions, the internal charge pump and the drivers will be shut down. otherwise, the system automati - cally comes online. this feature allows design engineers to address power saving concerns without major design changes. theory of operation the sp3243e series is made up of four basic circuit blocks: 1. drivers 2. receivers 3. the exar proprietary charge pump, and 4. auto on-line ? circuitry. drivers the drivers are inverting level transmitters that convert ttl or cmos logic levels to 5.0v eia/ tia-232 levels with an inverted sense relative to the input logic levels. typically, the rs-232 output voltage swing is + 5.4v with no load and + 5v minimum fully loaded. the driver outputs are protected against infnite short-circuits to ground without degradation in reliability. these drivers comply with the eia-tia-232-f and all previous rs-232 versions. unused drivers inputs should be connected to gnd or v cc . the drivers have a minimum data rate of 250kbps (eb) or 1000kbps (eu) fully loaded. figure 11 shows a loopback test circuit used to test the rs-232 drivers. figure 12 shows the test results where one driver was active at 1mbps and all three drivers loaded with an rs-232 re - ceiver in parallel with a 250pf capacitor. figure 13 shows the test results of the loopback circuit with all drivers active at 250kbps with typical rs-232 loads in parallel with 1000pf capacitors. a superior rs-232 data transmission rate of 1mbps makes the sp3243eu an ideal match for high speed lan and personal computer peripheral applications. figure 10. interface circuitry controlled by micropro - cessor supervisory circuit sp3243 e 28 24 2 1 27 3 26 5k ? 5k ? 5k ? 5k ? 5k ? gn d c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0. 1 f 0. 1 f 0. 1 f + c2 c5 c1 + + c3 c4 + + 0. 1 f 0. 1 f 9 10 11 4 5 6 7 8 rs-232 outputs rs-232 inputs 23 22 21 v cc 25 t 1 in r 1 ou t r 1 in t 2 ou t r 2 out t 2 in t 3 in t 3 ou t t 1 ou t r 2 in r 3 in r 4 in r 5 in r 2 out r 3 ou t r 4 ou t r 5 ou t onlin e shutdo wn st at us ua rt or ser ial c p super visor ic txd rt s dtr rxd cts dsr dcd ri v cc v in reset
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 9 receivers the receivers convert + 5.0v eia/tia-232 levels to ttl or cmos logic output levels. re - ceivers are high-z when the auto on-line ? circuitry is enabled or when in shutdown. the truth table logic of the sp3243 driver and receiver outputs can be found in table 2. the sp3243e includes an additional non-in - verting receiver with an output r 2 out. r 2 out is an extra output that remains active and monitors activity while the other receiver outputs are forced into high impedance. this allows a ring indicator (ri) signal from a peripheral to be monitored without forward biasing the ttl/cmos inputs of the other devices connected to the receiver outputs. table 2. shutdown truth tables note: in auto on-line ? mode where online = gnd and shutdown = v cc , the device will shut down if there is no activity present at the receiver inputs. figure 11. loopback test circuit for rs-232 driver data transmission rates since receiver input is usually from a transmis - sion line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mv. this ensures that the receiver is virtually immune to noisy transmission lines. should an input be left unconnected, an internal 5k? pulldown resistor to ground will commit the output of the receiver to a high state. figure 13. loopback test results at 250kbps figure 12. loopback test results at 1mbps sp3243 gnd t 1 in t x in c1+ c1- c2+ c2- v+ v- v cc 0. 1 f 0. 1 f 0. 1 f + c2 c5 c1 + + c3 c4 + + 0. 1 f 0. 1 f ttl/cmos inputs +3v to +5v 18 shutdo w n 5k ? r 1 out 5k ? r x in r x out ttl/cmos outputs online r 1 in t x out t 1 out st a tus v cc to p supervisor circuit 1000pf 1000pf device: sp3243e shutdown txout rxout r2out 0 high-z high-z active 1 active active active
10 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 charge pump the charge pump is a exarCpatented design (u.s. 5,306,954) and uses a unique approach compared to older lessCefficient designs. the charge pump still requires four external capacitors, but uses a fourCphase voltage shifting technique to attain symmetrical 5.5v power supplies. the internal power supply consists of a regulated dual charge pump that provides output voltages 5.5v regardless of the input voltage (v cc ) over the +3.0v to +5.5v range. this is important to maintain compli - ant rs-232 levels regardless of power supply fuctuations. the charge pump operates in a discontinuous mode using an internal oscillator. if the output voltages are less than a magnitude of 5.5v, the charge pump is enabled. if the output voltages exceed a magnitude of 5.5v, the charge pump is disabled. this oscillator controls the four phases of the voltage shifting. a description of each phase follows. phase 1 v ss charge storage during this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to v cc . c l + is then switched to gnd and the charge in c 1 C is transferred to c 2 C . since c 2 + is connected to v cc , the voltage potential across capacitor c 2 is now 2 times v cc . phase 2 v ss transfer phase two of the clock connects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to gnd. this transfers a negative gener - ated voltage to c 3 . this generated voltage is regulated to a minimum voltage of -5.5v. simultaneous with the transfer of the voltage to c 3 , the positive side of capacitor c 1 is switched to v cc and the negative side is connected to gnd. phase 3 v dd charge storage the third phase of the clock is identical to the frst phase the charge transferred in c 1 produces Cv cc in the negative terminal of c 1 , which is applied to the negative side of capacitor c 2 . since c 2 + is at v cc , the volt - age potential across c 2 is 2 times v cc . phase 4 v dd transfer the fourth phase of the clock connects the negative terminal of c 2 to gnd, and transfers this positive generated voltage across c 2 to c 4 , the v dd storage capacitor. this voltage is regulated to +5.5v. at this voltage, the internal oscillator is disabled. simultane - ous with the transfer of the voltage to c 4 , the positive side of capacitor c 1 is switched to v cc and the negative side is connected to gnd, al - lowing the charge pump cycle to begin again. the charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. since both v + and v C are separately generated from v cc , in a noCload condition v + and v C will be symmetrical. older charge pump approaches that generate v C from v + will show a decrease in the magnitude of v C compared to v + due to the inherent ineffciencies in the design. the clock rate for the charge pump typically operates at greater than 250khz. the external capacitors can be as low as 0.1f with a 16v breakdown voltage rating.
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 11 the sp3243e devices have a patent pending auto on-line ? circuitry on board that saves power in applications such as laptop computers, palmtop (pda) computers and other portable systems. the sp3243e devices incorporate an auto on-line ? circuit that automatically enables itself when the external transmitters are enabled and the cable is connected. conversely, the auto on-line ? circuit also disables most of the inter - nal circuitry when the device is not being used and goes into a standby mode where the device typically draws 1a. this function is externally controlled by the online pin. when this pin is tied to a logic low, the auto on-line ? function is active. once active, the device is enabled until there is no activity on the receiver inputs. the receiver input typically sees at least + 3v, which are generated from the transmitters at the other end of the cable with a + 5v minimum. minimum recommended charge pump capacitor value input voltage vcc charge pump capacitor value for sp32xx 3.0v to 3.6v c1 - c4 = 0.1f 4.5v to 5.5v c1 = 0.047f, c2 - c4 = 0.33f 3.0v to 5.5v c1 - c4 = 0.22f when the external transmitters are disabled or the cable is disconnected, the receiver inputs will be pulled down by their internal 5k? resistors to ground. when this occurs over a period of time, the internal transmitters will be disabled and the device goes into a shutdown or standy mode. when online is high, the auto on-line ? mode is disabled. the auto on-line ? circuit has two stages: 1) inactive detection 2) accumulated delay auto online circuitry the exar-patented charge pumps are designed to operate reliably with a range of low cost capacitors. either polarized or non polarized capacitors may be used. if polarized capacitors are used they should be oriented as shown in the typical operating circuit. the v+ capaci - tor may be connected to either ground or vcc (polarity reversed.) the charge pump operates with 0.1f capacitors for 3.3v operation. for other supply voltages, see the table for required capacitor values. do not use values smaller than those listed. increasing the capacitor values (e.g., by doubling in value) reduces ripple on the transmitter outputs and may slightly reduce power consumption. c2, c3, and c4 can be increased without changing c1s value. for best charge pump effciency locate the charge pump and bypass capacitors as close as possible to the ic. surface mount capacitors are best for this purpose. using capacitors with lower equivalent series resistance (esr) and self-inductance, along with minimizing parasitic pcb trace inductance will optimize charge pump operation. designers are also advised to consider that capacitor values may shift over time and operating temperature.
12 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 the frst stage, shown in figure 21, detects an inactive input. a logic high is asserted on r x inact if the cable is disconnected or the external transmitters are disabled. otherwise, r x inact will be at a logic low. this circuit is duplicated for each of the other receivers. the second stage of the auto on-line ? circuitry, shown in figure 22, processes all the receiver's r x inact signals with an accumulated delay that disables the device to a 1a supply current. the status pin goes to a logic low when the cable is disconnected, the external transmit - ters are disabled, or the shutdown pin is invoked. the typical accumulated delay is around 20s. when the sp3243e drivers or internal charge pump are disabled, the supply current is reduced to 1a. this can commonly occur in hand-held or portable applications where the rs-232 cable is disconnected or the rs-232 drivers of the con - nected peripheral are turned off. the auto on-line ? mode can be disabled by the shutdown pin. if this pin is a logic low, the auto on-line ? function will not operate regardless of the logic state of the online pin. table 3 summarizes the logic of the auto on- line ? operating modes. the truth table logic of the sp3243e driver and receiver outputs can be found in table 2. the status pin outputs a logic low signal if the device is shutdown. this pin goes to a logic high when the external transmitters are enabled and the cable is connected. when the sp3243e devices are shut down, the charge pumps are turned off. v+ charge pump output decays to v cc , the v- output decays to gnd. the decay time will depend on the size of capacitors used for the charge pump. once in shutdown, the time required to exit the shut down state and have valid v+ and v- levels is typically 200s. for easy programming, the status can be used to indicate dsr or a ring indicator sig - nal. tying online and shutdown together will bypass the auto on-line ? circuitry so this connection acts like a shutdown input pin. figure 14. auto on-line ? timing waveforms receiver rs-232 input vo lt ages s ta tus +5v 0v -5v t stsl t stsh t online v cc 0v driver rs-232 output vo lt ages 0v +2.7v -2.7v s h u t d o w n
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 13 figure 16. charge pump phase 2 v cc = +5 v v ss storage capacitor v dd storage capacit o r c 1 c 2 c 3 c 4 + + + + ? ? ? ? -5.5v v cc = +5v ?5v ?5v +5v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + + + ? ? ? ? figure 15. charge pump phase 1 figure 17. charge pump phase 3 v cc = +5v ?5v ?5v +5v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + + + ? ? ? ? figure 18. charge pump phase 4 v cc = +5 v v ss storage capacitor v dd storage capacit o r c 1 c 2 c 3 c 4 + + + + ? ? ? ? +5.5v
14 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 figure 19. sp3243e driver output voltages vs. load current per transmitter figure 20. circuit for the connectivity of the sp3243e with a db-9 connector 6 4 2 0 -2 -4 -6 transmitter output v oltage [v] load current per transmitter [ma] v out+ v out- 0.62 0.869 0.939 1.02 1.12 1.23 1.38 1.57 1.82 2.67 3.46 4.93 8.6 the sp3243e driver outputs are able to maintain voltage under loading of up to 2.5ma per driver, ensuring suffcient output for mouse-driving ap - plications. 6 7 8 9 1 2 3 4 5 db-9 connector 6. dce ready 7. request to send 8. clear to send 9. ring indicator db-9 connector pins: 1. receiv ed line signal detector 2. receiv ed data 3. tr ansmitted data 4. data te r minal ready 5. signal ground (common) sp3243e 28 24 2 1 27 3 26 5k 5k 5k 5k 5k gnd c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0. 1 f 0. 1 f 0. 1 f + c2 c5 c1 + + c3 c4 + + 0. 1 f 0. 1 f 9 10 11 4 5 6 7 8 to p super viso r circui t 23 22 21 v cc v cc 25 t 1 in r 1 ou t r 1 in t 2 out r 2 ou t t 2 in t 3 in t 3 out t 1 out r 2 in r 3 in r 4 in r 5 in r 2 ou t r 3 ou t r 4 ou t r 5 ou t onlin e shutdo wn s tat us 0 + v ou t v ou t - 1 0
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 15 l a n g i s 2 3 2 - s r r e v i e c e r t a t u p n i n w o d t u h s t u p n i t u p n i e n i l n u t p t u o s u t a t s r e v i e c s n a r t s u t a t s yes high h g i h n o i t a r e p o l a m r o n o n h g i h h g i h w o l n o i t a r e p o l a m r o n o n h g i h w o l w o l n w o d t u h s ( e n i l n o - o t u a ) low h g i h n w o d t u h s w o l n w o d t u h s low low yes high / lo w high / lo w no (auto-online ) o table 3. auto on-line ? logic figure 21. stage i of auto on-line ? circuitry figure 22. stage ii of auto on-line ? circuitry rs-232 recei v er block r x inact inactive detection block r x in r x out r 1 inact r 2 inact r 3 inact r 4 inact r 5 inact delay stage delay stage delay stage delay stage delay stage shutdow n st a tus
16 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 esd t olerance the sp3243e series incorporates ruggedized esd cells on all driver output and receiver input pins. the esd structure is improved over our previous family for more rugged applications and environments sensitive to electro-static dis - charges and associated transients. the improved esd tolerance is at least + 15kv without damage nor latch-up. there are different methods of esd testing ap - plied: a) mil-std-883, method 3015.7 b) iec1000-4-2 air-discharge c) iec1000-4-2 direct contact the human body model has been the generally accepted esd testing method for semi-con - ductors. this method is also specified in mil-std-883, method 3015.7 for esd testing. the premise of this esd test is to simulate the human bodys potential to store electro-static energy and discharge it to an integrated circuit. the simulation is performed by using a test model as shown in figure 23. this method will test the ics capability to withstand an esd transient during normal handling such as in manufacturing areas where the ics tend to be handled frequently. the iec-1000-4-2, formerly iec801-2, is generally used for testing esd on equipment and systems. for system manufacturers, they must guarantee a certain amount of esd protection since the system itself is exposed to the outside environment and human presence. the premise with iec1000-4- 2 is that the system is required to withstand an amount of static electricity when esd is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. the transceiver ic receives most of the esd current when the esd source is applied to the connector pins. the test circuit for iec1000-4-2 is shown on figure 24. there are two methods within iec1000-4-2, the air discharge method and the contact discharge method. with the air discharge method, an esd voltage is applied to the equipment under test (eut) through air. this simulates an electrically charged person ready to connect a cable onto the rear of the system only to fnd an unpleasant zap just before the person touches the back panel. the high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the sys - tem. this energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. variables with an air discharge such as approach speed of the object carrying the esd potential to the system and humidity will tend to change the discharge current. for example, the rise time of the discharge current varies with the approach speed. the contact discharge method applies the esd current directly to the eut. this method was devised to reduce the unpredictability of the esd arc. the discharge current rise time is constant since the energy is directly transferred without the air-gap arc. in situations such as hand held sys - tems, the esd charge can be directly discharged to the equipment from a person already holding the equipment. the current is transferred on to the keypad or the serial port of the equipment directly and then travels through the pcb and fnally to the ic. figure 23. esd test circuit for human body model r c devic e under test dc power sourc e c s r s sw1 sw2
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 17 device pin human b ody iec1000-4-2 tested model air discharge direct contact level driver outputs + 15kv + 15kv + 8kv 4 receiver inputs + 15kv + 15kv + 8kv 4 the circuit models in figures 23 and 24 represent the typical esd testing circuit used for all three methods. the c s is initially charged with the dc power supply when the frst switch (sw1) is on. now that the capacitor is charged, the second switch (sw2) is on while sw1 switches off. the voltage stored in the capacitor is then applied through r s , the current limiting resistor, onto the device under test (dut). in esd tests, the sw2 switch is pulsed so that the device under test receives a duration of voltage. for the human body model, the current limiting resistor (r s ) and the source capacitor (c s ) are 1.5k? an 100pf, respectively. for iec-1000-4-2, the current limiting resistor (r s ) and the source ca - pacitor (c s ) are 330? an 150pf, respectively. the higher c s value and lower r s value in the iec1000-4-2 model are more stringent than the human body model. the larger storage capaci - tor injects a higher voltage to the test point when sw2 is switched on. the lower current limiting resistor increases the current charge onto the test point. figure 25. esd test waveform for iec1000-4-2 figure 24. esd test circuit for iec1000-4-2 table 4. transceiver esd tolerance levels r s an d r v add up to 330 for iec1000-4-2. r c device unde r test dc power sourc e c s r s sw1 sw2 r v contact-discharge model t = 0ns t = 30ns 0a 15a 30a i t
18 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 package: 28 pin wsoic
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 19 package: 32 pin qfn
20 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 package: 28 pin ssop e
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 21 package: 28 pin tssop
22 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 sp 3243 e u ey l /tr t ape and reel options ?l? suffix indicates lead free packaging package type a= ssop y= tssop t emperature range c= commercial range 0oc to 70oc e= extended range -40oc to 85oc speed indicator blank= 120kbps b= 250kbps u= 1mbps esd rating e= 15kv hbm and iec 1000- 4 part number h= 460kbps t= wsoic r= qfn product nomenclature
exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 23 ordering information for tape and reel option add "/tr", example: sp3243eca-l/tr. part number data rate (kbps) temp. range package sp3243eca-l 120 0c to +70c 28 pin ssop sp3243ect-l 120 0c to +70c 28 pin wsoic sp3243ecy-l 120 0c to +70c 28 pin tssop sp3243eea-l 120 -40c to +85c 28 pin ssop sp3243eet-l 120 -40c to +85c 28 pin wsoic sp3243eey-l 120 -40c to +85c 28 pin tssop sp3243ebca-l 250 0c to +70c 28 pin ssop sp3243ebct-l 250 0c to +70c 28 pin wsoic sp3243ebcy-l 250 0c to +70c 28 pin tssop sp3243eber-l 250 0c to +70c 32 pin qfn sp3243ebea-l 250 -40c to +85c 28 pin ssop sp3243ebet-l 250 -40c to +85c 28 pin wsoic sp3243ebey-l 250 -40c to +85c 28 pin tssop sp3243eber-l 250 -40c to +85c 32 pin qfn sp3243ehca-l 460 0c to +70c 28 pin ssop sp3243ehct-l 460 0c to +70c 28 pin wsoic sp3243ehea-l 460 -40c to +85c 28 pin ssop sp3243ehet-l 460 -40c to +85c 28 pin wsoic sp3243euca-l 1000 0c to +70c 28 pin ssop sp3243euct-l 1000 0c to +70c 28 pin wsoic sp3243eucy-l 1000 0c to +70c 28 pin tssop sp3243euer-l 1000 0c to +70c 32 pin qfn sp3243euea-l 1000 -40c to +85c 28 pin ssop sp3243euet-l 1000 -40c to +85c 28 pin wsoic sp3243euey-l 1000 -40c to +85c 28 pin tssop sp3243euer-l 1000 -40c to +85c 32 pin qfn
24 exar corporation 48720 kato road, fremont ca, 94538 ? 510-668-7017 ? www.exar.com sp3243e_101_111009 revision history notice exar corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reli - ability. exar corporation assumes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specifc application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly af fect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2009 exar corporation datasheet november 2009 send your interface technical inquiry with technical details to: uarttechsupport@exar .com reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. date revision description 02/05/06 -- legacy sipex datasheet 07/23/09 1.0.0 convert to exar format, update ordering information and change revision to 1.0.0. 11/10/09 1.0.1 add missing (eh) model identifcation for driver output skew and transition-region slew rate specifcation and change revision to 1.0.1.

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